1. Field of the Invention
The present invention relates to a synchronous memory device, and more particularly, to a wave pipelined output circuit of a synchronous memory device.
2. Description of the Related Art
In general, a synchronous memory device uses various pipeline structures to increase a data output rate on a data output path. Among the various pipeline structures, a wave pipeline structure using a plurality of registers in an output circuit has a relatively simple circuit, occupies a small chip area and increases the operating speed of the circuit so that it is widely used in the synchronous memory device. An example of a conventional synchronous memory device having a general pipeline structure is disclosed in U.S. Pat. No. 5,384,737.
FIG. 1 is a block diagram of a conventional wave pipelined synchronous memory device. Referring to FIG. 1, the conventional wave pipelined synchronous memory device includes a memory cell array 11, a bitline sense amplifier 12, a column selecting gate 13, an input/output line sense amplifier 14, a burst ordering unit 15, and a wave pipelined output circuit 16.
The wave pipelined output circuit 16 latches data DATA_IN0 through DATA_IN3 which are read from the memory cell array 11 and inputted thereto in parallel via the bitline sense amplifier 12, the column selecting gate 13, the input/output line sense amplifier 14 and the burst ordering unit 15 in response to a plurality of latch control signals DL0 through DL3 and outputs the latched data as output data DATA_OUT in response to a plurality of output control signals CDQ_F/CDQ_S. The output data DATA_OUT is output to the outside via an output buffer (not shown) and an output pin (not shown).
FIG. 2 illustrates the configuration of the wave pipelined output circuit 16 of FIG. 1, and FIG. 3 is a timing diagram of the output circuit. Referring to FIG. 2, the output circuit 16 includes input multiplexers 211, 212, 213 and 214, registers 231 through 246, and output multiplexers 251, 252, 253 and 254. In FIG. 2, data DATA_IN inputted in parallel is 4-bit data and the number of the registers is 16.
Each of the input multiplexers 211, 212, 213 and 214 receives corresponding input data and outputs the input data to corresponding four registers in response to four latch control signals DL0, DL1, DL2 and DL3. Each of the output multiplexers 251, 252, 253 and 254 sequentially outputs the data latched in the corresponding four registers to a node DOFi or DOSi in response to corresponding four first output control signals CDQ_F or four second output control signals CDQ_S. For example, the input multiplexer 211 receives input data DATA_IN0 and outputs the input data DATA_IN0 to the four registers 231, 232, 233 and 234 in response to the four latch control signals DL0, DL1, DL2 and DL3. The output multiplexer 251 sequentially outputs the data latched in the four registers 231, 232, 233 and 234 to the node DOFi in response to the four first output control signals CDQ0_F, CDQ2_F, CDQ4_F and CDQ6_F.
The data of the node DOFi are sequentially output as output data DATA_OUT in response to a first output clock signal CLKDQ_F and the data of the node DOSi are sequentially output as output data DATA_OUT in response to a second output clock signal CLKDQ_S.
The number of the registers included in the wave pipelined output circuit is determined by maximum column address strobe (CAS) latency. The CAS latency represents the number of cycles of an operating clock signal included in a period of time from application of a read command to the synchronous memory device till output of data to the outside.
However, the number of the registers included in the wave pipelined output circuit is rapidly increased because the output circuit should operate in a wide frequency range from a high frequency to a low frequency. The increment in the number of the registers increases loads of data output paths in the output circuit to restrict a high frequency operation and augments the chip area of the output circuit.